// nios2soc.v

// Generated using ACDS version 14.1 186 at 2018.04.05.15:00:12

`timescale 1 ps / 1 ps
module nios2soc (
		input  wire        clk_clk,                                             //                                clk.clk
		input  wire [15:0] cy7c68013a_if_module_0_conduit_end_cha_fifo_data,    // cy7c68013a_if_module_0_conduit_end.cha_fifo_data
		input  wire        cy7c68013a_if_module_0_conduit_end_cha_fifo_rdempty, //                                   .cha_fifo_rdempty
		output wire        cy7c68013a_if_module_0_conduit_end_cha_fifo_rdreq,   //                                   .cha_fifo_rdreq
		input  wire [15:0] cy7c68013a_if_module_0_conduit_end_chb_fifo_data,    //                                   .chb_fifo_data
		input  wire        cy7c68013a_if_module_0_conduit_end_chb_fifo_rdempty, //                                   .chb_fifo_rdempty
		output wire        cy7c68013a_if_module_0_conduit_end_chb_fifo_rdreq,   //                                   .chb_fifo_rdreq
		input  wire [15:0] cy7c68013a_if_module_0_conduit_end_la_fifo_data,     //                                   .la_fifo_data
		input  wire        cy7c68013a_if_module_0_conduit_end_la_fifo_rdempty,  //                                   .la_fifo_rdempty
		output wire        cy7c68013a_if_module_0_conduit_end_la_fifo_rdreq,    //                                   .la_fifo_rdreq
		input  wire        cy7c68013a_if_module_0_conduit_end_flaga_raw,        //                                   .flaga_raw
		input  wire        cy7c68013a_if_module_0_conduit_end_flagc_raw,        //                                   .flagc_raw
		input  wire        cy7c68013a_if_module_0_conduit_end_flagb_raw,        //                                   .flagb_raw
		output wire        cy7c68013a_if_module_0_conduit_end_slwr,             //                                   .slwr
		output wire        cy7c68013a_if_module_0_conduit_end_slrd,             //                                   .slrd
		output wire        cy7c68013a_if_module_0_conduit_end_sloe,             //                                   .sloe
		output wire        cy7c68013a_if_module_0_conduit_end_pktend,           //                                   .pktend
		output wire [1:0]  cy7c68013a_if_module_0_conduit_end_fifoadr,          //                                   .fifoadr
		inout  wire [15:0] cy7c68013a_if_module_0_conduit_end_fd,               //                                   .fd
		output wire        cy7c68013a_if_module_0_conduit_end_soc_ready,        //                                   .soc_ready
		inout  wire [31:0] pio_0_external_connection_export,                    //          pio_0_external_connection.export
		input  wire        reset_reset_n,                                       //                              reset.reset_n
		output wire [15:0] scope_module_0_conduit_end_chb_fifo_data,            //         scope_module_0_conduit_end.chb_fifo_data
		output wire        scope_module_0_conduit_end_chb_fifo_rdempty,         //                                   .chb_fifo_rdempty
		input  wire        scope_module_0_conduit_end_chb_fifo_rdreq,           //                                   .chb_fifo_rdreq
		output wire [15:0] scope_module_0_conduit_end_cha_fifo_data,            //                                   .cha_fifo_data
		output wire        scope_module_0_conduit_end_cha_fifo_rdempty,         //                                   .cha_fifo_rdempty
		input  wire        scope_module_0_conduit_end_cha_fifo_rdreq,           //                                   .cha_fifo_rdreq
		output wire        scope_module_0_conduit_end_adc_clk,                  //                                   .adc_clk
		input  wire [7:0]  scope_module_0_conduit_end_chb_data,                 //                                   .chb_data
		input  wire [7:0]  scope_module_0_conduit_end_cha_data,                 //                                   .cha_data
		input  wire        spi_0_external_MISO,                                 //                     spi_0_external.MISO
		output wire        spi_0_external_MOSI,                                 //                                   .MOSI
		output wire        spi_0_external_SCLK,                                 //                                   .SCLK
		output wire [2:0]  spi_0_external_SS_n                                  //                                   .SS_n
	);

	wire  [31:0] nios2_gen2_0_data_master_readdata;                          // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
	wire         nios2_gen2_0_data_master_waitrequest;                       // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
	wire         nios2_gen2_0_data_master_debugaccess;                       // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
	wire  [21:0] nios2_gen2_0_data_master_address;                           // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
	wire   [3:0] nios2_gen2_0_data_master_byteenable;                        // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
	wire         nios2_gen2_0_data_master_read;                              // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
	wire         nios2_gen2_0_data_master_write;                             // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
	wire  [31:0] nios2_gen2_0_data_master_writedata;                         // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
	wire  [31:0] nios2_gen2_0_instruction_master_readdata;                   // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
	wire         nios2_gen2_0_instruction_master_waitrequest;                // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
	wire  [15:0] nios2_gen2_0_instruction_master_address;                    // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
	wire         nios2_gen2_0_instruction_master_read;                       // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
	wire  [31:0] mm_interconnect_0_epcq_controller_0_avl_csr_readdata;       // epcq_controller_0:avl_csr_rddata -> mm_interconnect_0:epcq_controller_0_avl_csr_readdata
	wire         mm_interconnect_0_epcq_controller_0_avl_csr_waitrequest;    // epcq_controller_0:avl_csr_waitrequest -> mm_interconnect_0:epcq_controller_0_avl_csr_waitrequest
	wire   [2:0] mm_interconnect_0_epcq_controller_0_avl_csr_address;        // mm_interconnect_0:epcq_controller_0_avl_csr_address -> epcq_controller_0:avl_csr_addr
	wire         mm_interconnect_0_epcq_controller_0_avl_csr_read;           // mm_interconnect_0:epcq_controller_0_avl_csr_read -> epcq_controller_0:avl_csr_read
	wire         mm_interconnect_0_epcq_controller_0_avl_csr_readdatavalid;  // epcq_controller_0:avl_csr_rddata_valid -> mm_interconnect_0:epcq_controller_0_avl_csr_readdatavalid
	wire         mm_interconnect_0_epcq_controller_0_avl_csr_write;          // mm_interconnect_0:epcq_controller_0_avl_csr_write -> epcq_controller_0:avl_csr_write
	wire  [31:0] mm_interconnect_0_epcq_controller_0_avl_csr_writedata;      // mm_interconnect_0:epcq_controller_0_avl_csr_writedata -> epcq_controller_0:avl_csr_wrdata
	wire  [31:0] mm_interconnect_0_epcq_controller_0_avl_mem_readdata;       // epcq_controller_0:avl_mem_rddata -> mm_interconnect_0:epcq_controller_0_avl_mem_readdata
	wire         mm_interconnect_0_epcq_controller_0_avl_mem_waitrequest;    // epcq_controller_0:avl_mem_waitrequest -> mm_interconnect_0:epcq_controller_0_avl_mem_waitrequest
	wire  [18:0] mm_interconnect_0_epcq_controller_0_avl_mem_address;        // mm_interconnect_0:epcq_controller_0_avl_mem_address -> epcq_controller_0:avl_mem_addr
	wire         mm_interconnect_0_epcq_controller_0_avl_mem_read;           // mm_interconnect_0:epcq_controller_0_avl_mem_read -> epcq_controller_0:avl_mem_read
	wire   [3:0] mm_interconnect_0_epcq_controller_0_avl_mem_byteenable;     // mm_interconnect_0:epcq_controller_0_avl_mem_byteenable -> epcq_controller_0:avl_mem_byteenable
	wire         mm_interconnect_0_epcq_controller_0_avl_mem_readdatavalid;  // epcq_controller_0:avl_mem_rddata_valid -> mm_interconnect_0:epcq_controller_0_avl_mem_readdatavalid
	wire         mm_interconnect_0_epcq_controller_0_avl_mem_write;          // mm_interconnect_0:epcq_controller_0_avl_mem_write -> epcq_controller_0:avl_mem_write
	wire  [31:0] mm_interconnect_0_epcq_controller_0_avl_mem_writedata;      // mm_interconnect_0:epcq_controller_0_avl_mem_writedata -> epcq_controller_0:avl_mem_wrdata
	wire   [6:0] mm_interconnect_0_epcq_controller_0_avl_mem_burstcount;     // mm_interconnect_0:epcq_controller_0_avl_mem_burstcount -> epcq_controller_0:avl_mem_burstcount
	wire  [31:0] mm_interconnect_0_sysid_qsys_0_control_slave_readdata;      // sysid_qsys_0:readdata -> mm_interconnect_0:sysid_qsys_0_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_qsys_0_control_slave_address;       // mm_interconnect_0:sysid_qsys_0_control_slave_address -> sysid_qsys_0:address
	wire  [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata;    // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
	wire         mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
	wire         mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address;     // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
	wire         mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read;        // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
	wire   [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable;  // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
	wire         mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write;       // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
	wire  [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata;   // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
	wire  [31:0] mm_interconnect_0_scope_module_0_s0_readdata;               // scope_module_0:avs_s0_readdata -> mm_interconnect_0:scope_module_0_s0_readdata
	wire         mm_interconnect_0_scope_module_0_s0_waitrequest;            // scope_module_0:avs_s0_waitrequest -> mm_interconnect_0:scope_module_0_s0_waitrequest
	wire   [7:0] mm_interconnect_0_scope_module_0_s0_address;                // mm_interconnect_0:scope_module_0_s0_address -> scope_module_0:avs_s0_address
	wire         mm_interconnect_0_scope_module_0_s0_read;                   // mm_interconnect_0:scope_module_0_s0_read -> scope_module_0:avs_s0_read
	wire         mm_interconnect_0_scope_module_0_s0_write;                  // mm_interconnect_0:scope_module_0_s0_write -> scope_module_0:avs_s0_write
	wire  [31:0] mm_interconnect_0_scope_module_0_s0_writedata;              // mm_interconnect_0:scope_module_0_s0_writedata -> scope_module_0:avs_s0_writedata
	wire  [31:0] mm_interconnect_0_cy7c68013a_if_module_0_s0_readdata;       // cy7c68013a_if_module_0:avs_s0_readdata -> mm_interconnect_0:cy7c68013a_if_module_0_s0_readdata
	wire         mm_interconnect_0_cy7c68013a_if_module_0_s0_waitrequest;    // cy7c68013a_if_module_0:avs_s0_waitrequest -> mm_interconnect_0:cy7c68013a_if_module_0_s0_waitrequest
	wire   [7:0] mm_interconnect_0_cy7c68013a_if_module_0_s0_address;        // mm_interconnect_0:cy7c68013a_if_module_0_s0_address -> cy7c68013a_if_module_0:avs_s0_address
	wire         mm_interconnect_0_cy7c68013a_if_module_0_s0_read;           // mm_interconnect_0:cy7c68013a_if_module_0_s0_read -> cy7c68013a_if_module_0:avs_s0_read
	wire         mm_interconnect_0_cy7c68013a_if_module_0_s0_write;          // mm_interconnect_0:cy7c68013a_if_module_0_s0_write -> cy7c68013a_if_module_0:avs_s0_write
	wire  [31:0] mm_interconnect_0_cy7c68013a_if_module_0_s0_writedata;      // mm_interconnect_0:cy7c68013a_if_module_0_s0_writedata -> cy7c68013a_if_module_0:avs_s0_writedata
	wire         mm_interconnect_0_onchip_memory2_0_s1_chipselect;           // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
	wire  [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata;             // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
	wire  [10:0] mm_interconnect_0_onchip_memory2_0_s1_address;              // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
	wire   [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable;           // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
	wire         mm_interconnect_0_onchip_memory2_0_s1_write;                // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
	wire  [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata;            // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
	wire         mm_interconnect_0_onchip_memory2_0_s1_clken;                // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
	wire         mm_interconnect_0_pio_0_s1_chipselect;                      // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
	wire  [31:0] mm_interconnect_0_pio_0_s1_readdata;                        // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_0_s1_address;                         // mm_interconnect_0:pio_0_s1_address -> pio_0:address
	wire         mm_interconnect_0_pio_0_s1_write;                           // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
	wire  [31:0] mm_interconnect_0_pio_0_s1_writedata;                       // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
	wire         mm_interconnect_0_timer_0_s1_chipselect;                    // mm_interconnect_0:timer_0_s1_chipselect -> timer_0:chipselect
	wire  [15:0] mm_interconnect_0_timer_0_s1_readdata;                      // timer_0:readdata -> mm_interconnect_0:timer_0_s1_readdata
	wire   [2:0] mm_interconnect_0_timer_0_s1_address;                       // mm_interconnect_0:timer_0_s1_address -> timer_0:address
	wire         mm_interconnect_0_timer_0_s1_write;                         // mm_interconnect_0:timer_0_s1_write -> timer_0:write_n
	wire  [15:0] mm_interconnect_0_timer_0_s1_writedata;                     // mm_interconnect_0:timer_0_s1_writedata -> timer_0:writedata
	wire         mm_interconnect_0_spi_0_spi_control_port_chipselect;        // mm_interconnect_0:spi_0_spi_control_port_chipselect -> spi_0:spi_select
	wire  [15:0] mm_interconnect_0_spi_0_spi_control_port_readdata;          // spi_0:data_to_cpu -> mm_interconnect_0:spi_0_spi_control_port_readdata
	wire   [2:0] mm_interconnect_0_spi_0_spi_control_port_address;           // mm_interconnect_0:spi_0_spi_control_port_address -> spi_0:mem_addr
	wire         mm_interconnect_0_spi_0_spi_control_port_read;              // mm_interconnect_0:spi_0_spi_control_port_read -> spi_0:read_n
	wire         mm_interconnect_0_spi_0_spi_control_port_write;             // mm_interconnect_0:spi_0_spi_control_port_write -> spi_0:write_n
	wire  [15:0] mm_interconnect_0_spi_0_spi_control_port_writedata;         // mm_interconnect_0:spi_0_spi_control_port_writedata -> spi_0:data_from_cpu
	wire         irq_mapper_receiver0_irq;                                   // epcq_controller_0:irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                   // spi_0:irq -> irq_mapper:receiver1_irq
	wire         irq_mapper_receiver2_irq;                                   // timer_0:irq -> irq_mapper:receiver2_irq
	wire         irq_mapper_receiver3_irq;                                   // scope_module_0:ins_irq0_irq -> irq_mapper:receiver3_irq
	wire         irq_mapper_receiver4_irq;                                   // cy7c68013a_if_module_0:ins_irq0_irq -> irq_mapper:receiver4_irq
	wire  [31:0] nios2_gen2_0_irq_irq;                                       // irq_mapper:sender_irq -> nios2_gen2_0:irq
	wire         rst_controller_reset_out_reset;                             // rst_controller:reset_out -> [cy7c68013a_if_module_0:reset, epcq_controller_0:reset_n, irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_memory2_0:reset, pio_0:reset_n, rst_translator:in_reset, scope_module_0:reset, spi_0:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n]
	wire         rst_controller_reset_out_reset_req;                         // rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
	wire         nios2_gen2_0_debug_reset_request_reset;                     // nios2_gen2_0:debug_reset_request -> rst_controller:reset_in1

	cy7c68013a_if_module cy7c68013a_if_module_0 (
		.avs_s0_address     (mm_interconnect_0_cy7c68013a_if_module_0_s0_address),     //          s0.address
		.avs_s0_read        (mm_interconnect_0_cy7c68013a_if_module_0_s0_read),        //            .read
		.avs_s0_readdata    (mm_interconnect_0_cy7c68013a_if_module_0_s0_readdata),    //            .readdata
		.avs_s0_write       (mm_interconnect_0_cy7c68013a_if_module_0_s0_write),       //            .write
		.avs_s0_writedata   (mm_interconnect_0_cy7c68013a_if_module_0_s0_writedata),   //            .writedata
		.avs_s0_waitrequest (mm_interconnect_0_cy7c68013a_if_module_0_s0_waitrequest), //            .waitrequest
		.clk                (clk_clk),                                                 //       clock.clk
		.reset              (rst_controller_reset_out_reset),                          //       reset.reset
		.ins_irq0_irq       (irq_mapper_receiver4_irq),                                //        irq0.irq
		.cha_fifo_data      (cy7c68013a_if_module_0_conduit_end_cha_fifo_data),        // conduit_end.cha_fifo_data
		.cha_fifo_rdempty   (cy7c68013a_if_module_0_conduit_end_cha_fifo_rdempty),     //            .cha_fifo_rdempty
		.cha_fifo_rdreq     (cy7c68013a_if_module_0_conduit_end_cha_fifo_rdreq),       //            .cha_fifo_rdreq
		.chb_fifo_data      (cy7c68013a_if_module_0_conduit_end_chb_fifo_data),        //            .chb_fifo_data
		.chb_fifo_rdempty   (cy7c68013a_if_module_0_conduit_end_chb_fifo_rdempty),     //            .chb_fifo_rdempty
		.chb_fifo_rdreq     (cy7c68013a_if_module_0_conduit_end_chb_fifo_rdreq),       //            .chb_fifo_rdreq
		.la_fifo_data       (cy7c68013a_if_module_0_conduit_end_la_fifo_data),         //            .la_fifo_data
		.la_fifo_rdempty    (cy7c68013a_if_module_0_conduit_end_la_fifo_rdempty),      //            .la_fifo_rdempty
		.la_fifo_rdreq      (cy7c68013a_if_module_0_conduit_end_la_fifo_rdreq),        //            .la_fifo_rdreq
		.flaga_raw          (cy7c68013a_if_module_0_conduit_end_flaga_raw),            //            .flaga_raw
		.flagc_raw          (cy7c68013a_if_module_0_conduit_end_flagc_raw),            //            .flagc_raw
		.flagb_raw          (cy7c68013a_if_module_0_conduit_end_flagb_raw),            //            .flagb_raw
		.slwr               (cy7c68013a_if_module_0_conduit_end_slwr),                 //            .slwr
		.slrd               (cy7c68013a_if_module_0_conduit_end_slrd),                 //            .slrd
		.sloe               (cy7c68013a_if_module_0_conduit_end_sloe),                 //            .sloe
		.pktend             (cy7c68013a_if_module_0_conduit_end_pktend),               //            .pktend
		.fifoadr            (cy7c68013a_if_module_0_conduit_end_fifoadr),              //            .fifoadr
		.fd                 (cy7c68013a_if_module_0_conduit_end_fd),                   //            .fd
		.soc_ready          (cy7c68013a_if_module_0_conduit_end_soc_ready)             //            .soc_ready
	);

	altera_epcq_controller_wrapper #(
		.DEVICE_FAMILY     ("Cyclone IV E"),
		.ASI_WIDTH         (1),
		.CS_WIDTH          (1),
		.ADDR_WIDTH        (19),
		.ASMI_ADDR_WIDTH   (24),
		.ENABLE_4BYTE_ADDR (0),
		.CHIP_SELS         (1)
	) epcq_controller_0 (
		.clk                  (clk_clk),                                                   //       clock_sink.clk
		.reset_n              (~rst_controller_reset_out_reset),                           //            reset.reset_n
		.avl_csr_read         (mm_interconnect_0_epcq_controller_0_avl_csr_read),          //          avl_csr.read
		.avl_csr_waitrequest  (mm_interconnect_0_epcq_controller_0_avl_csr_waitrequest),   //                 .waitrequest
		.avl_csr_write        (mm_interconnect_0_epcq_controller_0_avl_csr_write),         //                 .write
		.avl_csr_addr         (mm_interconnect_0_epcq_controller_0_avl_csr_address),       //                 .address
		.avl_csr_wrdata       (mm_interconnect_0_epcq_controller_0_avl_csr_writedata),     //                 .writedata
		.avl_csr_rddata       (mm_interconnect_0_epcq_controller_0_avl_csr_readdata),      //                 .readdata
		.avl_csr_rddata_valid (mm_interconnect_0_epcq_controller_0_avl_csr_readdatavalid), //                 .readdatavalid
		.avl_mem_write        (mm_interconnect_0_epcq_controller_0_avl_mem_write),         //          avl_mem.write
		.avl_mem_burstcount   (mm_interconnect_0_epcq_controller_0_avl_mem_burstcount),    //                 .burstcount
		.avl_mem_waitrequest  (mm_interconnect_0_epcq_controller_0_avl_mem_waitrequest),   //                 .waitrequest
		.avl_mem_read         (mm_interconnect_0_epcq_controller_0_avl_mem_read),          //                 .read
		.avl_mem_addr         (mm_interconnect_0_epcq_controller_0_avl_mem_address),       //                 .address
		.avl_mem_wrdata       (mm_interconnect_0_epcq_controller_0_avl_mem_writedata),     //                 .writedata
		.avl_mem_rddata       (mm_interconnect_0_epcq_controller_0_avl_mem_readdata),      //                 .readdata
		.avl_mem_rddata_valid (mm_interconnect_0_epcq_controller_0_avl_mem_readdatavalid), //                 .readdatavalid
		.avl_mem_byteenable   (mm_interconnect_0_epcq_controller_0_avl_mem_byteenable),    //                 .byteenable
		.irq                  (irq_mapper_receiver0_irq)                                   // interrupt_sender.irq
	);

	nios2soc_nios2_gen2_0 nios2_gen2_0 (
		.clk                                 (clk_clk),                                                    //                       clk.clk
		.reset_n                             (~rst_controller_reset_out_reset),                            //                     reset.reset_n
		.reset_req                           (rst_controller_reset_out_reset_req),                         //                          .reset_req
		.d_address                           (nios2_gen2_0_data_master_address),                           //               data_master.address
		.d_byteenable                        (nios2_gen2_0_data_master_byteenable),                        //                          .byteenable
		.d_read                              (nios2_gen2_0_data_master_read),                              //                          .read
		.d_readdata                          (nios2_gen2_0_data_master_readdata),                          //                          .readdata
		.d_waitrequest                       (nios2_gen2_0_data_master_waitrequest),                       //                          .waitrequest
		.d_write                             (nios2_gen2_0_data_master_write),                             //                          .write
		.d_writedata                         (nios2_gen2_0_data_master_writedata),                         //                          .writedata
		.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess),                       //                          .debugaccess
		.i_address                           (nios2_gen2_0_instruction_master_address),                    //        instruction_master.address
		.i_read                              (nios2_gen2_0_instruction_master_read),                       //                          .read
		.i_readdata                          (nios2_gen2_0_instruction_master_readdata),                   //                          .readdata
		.i_waitrequest                       (nios2_gen2_0_instruction_master_waitrequest),                //                          .waitrequest
		.irq                                 (nios2_gen2_0_irq_irq),                                       //                       irq.irq
		.debug_reset_request                 (nios2_gen2_0_debug_reset_request_reset),                     //       debug_reset_request.reset
		.debug_mem_slave_address             (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address),     //           debug_mem_slave.address
		.debug_mem_slave_byteenable          (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable),  //                          .byteenable
		.debug_mem_slave_debugaccess         (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), //                          .debugaccess
		.debug_mem_slave_read                (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read),        //                          .read
		.debug_mem_slave_readdata            (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata),    //                          .readdata
		.debug_mem_slave_waitrequest         (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), //                          .waitrequest
		.debug_mem_slave_write               (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write),       //                          .write
		.debug_mem_slave_writedata           (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata),   //                          .writedata
		.dummy_ci_port                       ()                                                            // custom_instruction_master.readra
	);

	nios2soc_onchip_memory2_0 onchip_memory2_0 (
		.clk        (clk_clk),                                          //   clk1.clk
		.address    (mm_interconnect_0_onchip_memory2_0_s1_address),    //     s1.address
		.clken      (mm_interconnect_0_onchip_memory2_0_s1_clken),      //       .clken
		.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), //       .chipselect
		.write      (mm_interconnect_0_onchip_memory2_0_s1_write),      //       .write
		.readdata   (mm_interconnect_0_onchip_memory2_0_s1_readdata),   //       .readdata
		.writedata  (mm_interconnect_0_onchip_memory2_0_s1_writedata),  //       .writedata
		.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), //       .byteenable
		.reset      (rst_controller_reset_out_reset),                   // reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)                //       .reset_req
	);

	nios2soc_pio_0 pio_0 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_pio_0_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_pio_0_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_pio_0_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_pio_0_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_pio_0_s1_readdata),   //                    .readdata
		.bidir_port (pio_0_external_connection_export)       // external_connection.export
	);

	scope_module scope_module_0 (
		.avs_s0_read        (mm_interconnect_0_scope_module_0_s0_read),        //          s0.read
		.avs_s0_readdata    (mm_interconnect_0_scope_module_0_s0_readdata),    //            .readdata
		.avs_s0_write       (mm_interconnect_0_scope_module_0_s0_write),       //            .write
		.avs_s0_writedata   (mm_interconnect_0_scope_module_0_s0_writedata),   //            .writedata
		.avs_s0_address     (mm_interconnect_0_scope_module_0_s0_address),     //            .address
		.avs_s0_waitrequest (mm_interconnect_0_scope_module_0_s0_waitrequest), //            .waitrequest
		.clk                (clk_clk),                                         //       clock.clk
		.reset              (rst_controller_reset_out_reset),                  //       reset.reset
		.ins_irq0_irq       (irq_mapper_receiver3_irq),                        //        irq0.irq
		.chb_fifo_data      (scope_module_0_conduit_end_chb_fifo_data),        // conduit_end.chb_fifo_data
		.chb_fifo_rdempty   (scope_module_0_conduit_end_chb_fifo_rdempty),     //            .chb_fifo_rdempty
		.chb_fifo_rdreq     (scope_module_0_conduit_end_chb_fifo_rdreq),       //            .chb_fifo_rdreq
		.cha_fifo_data      (scope_module_0_conduit_end_cha_fifo_data),        //            .cha_fifo_data
		.cha_fifo_rdempty   (scope_module_0_conduit_end_cha_fifo_rdempty),     //            .cha_fifo_rdempty
		.cha_fifo_rdreq     (scope_module_0_conduit_end_cha_fifo_rdreq),       //            .cha_fifo_rdreq
		.adc_clk            (scope_module_0_conduit_end_adc_clk),              //            .adc_clk
		.chb_data           (scope_module_0_conduit_end_chb_data),             //            .chb_data
		.cha_data           (scope_module_0_conduit_end_cha_data)              //            .cha_data
	);

	nios2soc_spi_0 spi_0 (
		.clk           (clk_clk),                                             //              clk.clk
		.reset_n       (~rst_controller_reset_out_reset),                     //            reset.reset_n
		.data_from_cpu (mm_interconnect_0_spi_0_spi_control_port_writedata),  // spi_control_port.writedata
		.data_to_cpu   (mm_interconnect_0_spi_0_spi_control_port_readdata),   //                 .readdata
		.mem_addr      (mm_interconnect_0_spi_0_spi_control_port_address),    //                 .address
		.read_n        (~mm_interconnect_0_spi_0_spi_control_port_read),      //                 .read_n
		.spi_select    (mm_interconnect_0_spi_0_spi_control_port_chipselect), //                 .chipselect
		.write_n       (~mm_interconnect_0_spi_0_spi_control_port_write),     //                 .write_n
		.irq           (irq_mapper_receiver1_irq),                            //              irq.irq
		.MISO          (spi_0_external_MISO),                                 //         external.export
		.MOSI          (spi_0_external_MOSI),                                 //                 .export
		.SCLK          (spi_0_external_SCLK),                                 //                 .export
		.SS_n          (spi_0_external_SS_n)                                  //                 .export
	);

	nios2soc_sysid_qsys_0 sysid_qsys_0 (
		.clock    (clk_clk),                                               //           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                       //         reset.reset_n
		.readdata (mm_interconnect_0_sysid_qsys_0_control_slave_readdata), // control_slave.readdata
		.address  (mm_interconnect_0_sysid_qsys_0_control_slave_address)   //              .address
	);

	nios2soc_timer_0 timer_0 (
		.clk        (clk_clk),                                 //   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         // reset.reset_n
		.address    (mm_interconnect_0_timer_0_s1_address),    //    s1.address
		.writedata  (mm_interconnect_0_timer_0_s1_writedata),  //      .writedata
		.readdata   (mm_interconnect_0_timer_0_s1_readdata),   //      .readdata
		.chipselect (mm_interconnect_0_timer_0_s1_chipselect), //      .chipselect
		.write_n    (~mm_interconnect_0_timer_0_s1_write),     //      .write_n
		.irq        (irq_mapper_receiver2_irq)                 //   irq.irq
	);

	nios2soc_mm_interconnect_0 mm_interconnect_0 (
		.clk_0_clk_clk                                  (clk_clk),                                                    //                                clk_0_clk.clk
		.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                             // nios2_gen2_0_reset_reset_bridge_in_reset.reset
		.nios2_gen2_0_data_master_address               (nios2_gen2_0_data_master_address),                           //                 nios2_gen2_0_data_master.address
		.nios2_gen2_0_data_master_waitrequest           (nios2_gen2_0_data_master_waitrequest),                       //                                         .waitrequest
		.nios2_gen2_0_data_master_byteenable            (nios2_gen2_0_data_master_byteenable),                        //                                         .byteenable
		.nios2_gen2_0_data_master_read                  (nios2_gen2_0_data_master_read),                              //                                         .read
		.nios2_gen2_0_data_master_readdata              (nios2_gen2_0_data_master_readdata),                          //                                         .readdata
		.nios2_gen2_0_data_master_write                 (nios2_gen2_0_data_master_write),                             //                                         .write
		.nios2_gen2_0_data_master_writedata             (nios2_gen2_0_data_master_writedata),                         //                                         .writedata
		.nios2_gen2_0_data_master_debugaccess           (nios2_gen2_0_data_master_debugaccess),                       //                                         .debugaccess
		.nios2_gen2_0_instruction_master_address        (nios2_gen2_0_instruction_master_address),                    //          nios2_gen2_0_instruction_master.address
		.nios2_gen2_0_instruction_master_waitrequest    (nios2_gen2_0_instruction_master_waitrequest),                //                                         .waitrequest
		.nios2_gen2_0_instruction_master_read           (nios2_gen2_0_instruction_master_read),                       //                                         .read
		.nios2_gen2_0_instruction_master_readdata       (nios2_gen2_0_instruction_master_readdata),                   //                                         .readdata
		.cy7c68013a_if_module_0_s0_address              (mm_interconnect_0_cy7c68013a_if_module_0_s0_address),        //                cy7c68013a_if_module_0_s0.address
		.cy7c68013a_if_module_0_s0_write                (mm_interconnect_0_cy7c68013a_if_module_0_s0_write),          //                                         .write
		.cy7c68013a_if_module_0_s0_read                 (mm_interconnect_0_cy7c68013a_if_module_0_s0_read),           //                                         .read
		.cy7c68013a_if_module_0_s0_readdata             (mm_interconnect_0_cy7c68013a_if_module_0_s0_readdata),       //                                         .readdata
		.cy7c68013a_if_module_0_s0_writedata            (mm_interconnect_0_cy7c68013a_if_module_0_s0_writedata),      //                                         .writedata
		.cy7c68013a_if_module_0_s0_waitrequest          (mm_interconnect_0_cy7c68013a_if_module_0_s0_waitrequest),    //                                         .waitrequest
		.epcq_controller_0_avl_csr_address              (mm_interconnect_0_epcq_controller_0_avl_csr_address),        //                epcq_controller_0_avl_csr.address
		.epcq_controller_0_avl_csr_write                (mm_interconnect_0_epcq_controller_0_avl_csr_write),          //                                         .write
		.epcq_controller_0_avl_csr_read                 (mm_interconnect_0_epcq_controller_0_avl_csr_read),           //                                         .read
		.epcq_controller_0_avl_csr_readdata             (mm_interconnect_0_epcq_controller_0_avl_csr_readdata),       //                                         .readdata
		.epcq_controller_0_avl_csr_writedata            (mm_interconnect_0_epcq_controller_0_avl_csr_writedata),      //                                         .writedata
		.epcq_controller_0_avl_csr_readdatavalid        (mm_interconnect_0_epcq_controller_0_avl_csr_readdatavalid),  //                                         .readdatavalid
		.epcq_controller_0_avl_csr_waitrequest          (mm_interconnect_0_epcq_controller_0_avl_csr_waitrequest),    //                                         .waitrequest
		.epcq_controller_0_avl_mem_address              (mm_interconnect_0_epcq_controller_0_avl_mem_address),        //                epcq_controller_0_avl_mem.address
		.epcq_controller_0_avl_mem_write                (mm_interconnect_0_epcq_controller_0_avl_mem_write),          //                                         .write
		.epcq_controller_0_avl_mem_read                 (mm_interconnect_0_epcq_controller_0_avl_mem_read),           //                                         .read
		.epcq_controller_0_avl_mem_readdata             (mm_interconnect_0_epcq_controller_0_avl_mem_readdata),       //                                         .readdata
		.epcq_controller_0_avl_mem_writedata            (mm_interconnect_0_epcq_controller_0_avl_mem_writedata),      //                                         .writedata
		.epcq_controller_0_avl_mem_burstcount           (mm_interconnect_0_epcq_controller_0_avl_mem_burstcount),     //                                         .burstcount
		.epcq_controller_0_avl_mem_byteenable           (mm_interconnect_0_epcq_controller_0_avl_mem_byteenable),     //                                         .byteenable
		.epcq_controller_0_avl_mem_readdatavalid        (mm_interconnect_0_epcq_controller_0_avl_mem_readdatavalid),  //                                         .readdatavalid
		.epcq_controller_0_avl_mem_waitrequest          (mm_interconnect_0_epcq_controller_0_avl_mem_waitrequest),    //                                         .waitrequest
		.nios2_gen2_0_debug_mem_slave_address           (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address),     //             nios2_gen2_0_debug_mem_slave.address
		.nios2_gen2_0_debug_mem_slave_write             (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write),       //                                         .write
		.nios2_gen2_0_debug_mem_slave_read              (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read),        //                                         .read
		.nios2_gen2_0_debug_mem_slave_readdata          (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata),    //                                         .readdata
		.nios2_gen2_0_debug_mem_slave_writedata         (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata),   //                                         .writedata
		.nios2_gen2_0_debug_mem_slave_byteenable        (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable),  //                                         .byteenable
		.nios2_gen2_0_debug_mem_slave_waitrequest       (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), //                                         .waitrequest
		.nios2_gen2_0_debug_mem_slave_debugaccess       (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), //                                         .debugaccess
		.onchip_memory2_0_s1_address                    (mm_interconnect_0_onchip_memory2_0_s1_address),              //                      onchip_memory2_0_s1.address
		.onchip_memory2_0_s1_write                      (mm_interconnect_0_onchip_memory2_0_s1_write),                //                                         .write
		.onchip_memory2_0_s1_readdata                   (mm_interconnect_0_onchip_memory2_0_s1_readdata),             //                                         .readdata
		.onchip_memory2_0_s1_writedata                  (mm_interconnect_0_onchip_memory2_0_s1_writedata),            //                                         .writedata
		.onchip_memory2_0_s1_byteenable                 (mm_interconnect_0_onchip_memory2_0_s1_byteenable),           //                                         .byteenable
		.onchip_memory2_0_s1_chipselect                 (mm_interconnect_0_onchip_memory2_0_s1_chipselect),           //                                         .chipselect
		.onchip_memory2_0_s1_clken                      (mm_interconnect_0_onchip_memory2_0_s1_clken),                //                                         .clken
		.pio_0_s1_address                               (mm_interconnect_0_pio_0_s1_address),                         //                                 pio_0_s1.address
		.pio_0_s1_write                                 (mm_interconnect_0_pio_0_s1_write),                           //                                         .write
		.pio_0_s1_readdata                              (mm_interconnect_0_pio_0_s1_readdata),                        //                                         .readdata
		.pio_0_s1_writedata                             (mm_interconnect_0_pio_0_s1_writedata),                       //                                         .writedata
		.pio_0_s1_chipselect                            (mm_interconnect_0_pio_0_s1_chipselect),                      //                                         .chipselect
		.scope_module_0_s0_address                      (mm_interconnect_0_scope_module_0_s0_address),                //                        scope_module_0_s0.address
		.scope_module_0_s0_write                        (mm_interconnect_0_scope_module_0_s0_write),                  //                                         .write
		.scope_module_0_s0_read                         (mm_interconnect_0_scope_module_0_s0_read),                   //                                         .read
		.scope_module_0_s0_readdata                     (mm_interconnect_0_scope_module_0_s0_readdata),               //                                         .readdata
		.scope_module_0_s0_writedata                    (mm_interconnect_0_scope_module_0_s0_writedata),              //                                         .writedata
		.scope_module_0_s0_waitrequest                  (mm_interconnect_0_scope_module_0_s0_waitrequest),            //                                         .waitrequest
		.spi_0_spi_control_port_address                 (mm_interconnect_0_spi_0_spi_control_port_address),           //                   spi_0_spi_control_port.address
		.spi_0_spi_control_port_write                   (mm_interconnect_0_spi_0_spi_control_port_write),             //                                         .write
		.spi_0_spi_control_port_read                    (mm_interconnect_0_spi_0_spi_control_port_read),              //                                         .read
		.spi_0_spi_control_port_readdata                (mm_interconnect_0_spi_0_spi_control_port_readdata),          //                                         .readdata
		.spi_0_spi_control_port_writedata               (mm_interconnect_0_spi_0_spi_control_port_writedata),         //                                         .writedata
		.spi_0_spi_control_port_chipselect              (mm_interconnect_0_spi_0_spi_control_port_chipselect),        //                                         .chipselect
		.sysid_qsys_0_control_slave_address             (mm_interconnect_0_sysid_qsys_0_control_slave_address),       //               sysid_qsys_0_control_slave.address
		.sysid_qsys_0_control_slave_readdata            (mm_interconnect_0_sysid_qsys_0_control_slave_readdata),      //                                         .readdata
		.timer_0_s1_address                             (mm_interconnect_0_timer_0_s1_address),                       //                               timer_0_s1.address
		.timer_0_s1_write                               (mm_interconnect_0_timer_0_s1_write),                         //                                         .write
		.timer_0_s1_readdata                            (mm_interconnect_0_timer_0_s1_readdata),                      //                                         .readdata
		.timer_0_s1_writedata                           (mm_interconnect_0_timer_0_s1_writedata),                     //                                         .writedata
		.timer_0_s1_chipselect                          (mm_interconnect_0_timer_0_s1_chipselect)                     //                                         .chipselect
	);

	nios2soc_irq_mapper irq_mapper (
		.clk           (clk_clk),                        //       clk.clk
		.reset         (rst_controller_reset_out_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),       // receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),       // receiver1.irq
		.receiver2_irq (irq_mapper_receiver2_irq),       // receiver2.irq
		.receiver3_irq (irq_mapper_receiver3_irq),       // receiver3.irq
		.receiver4_irq (irq_mapper_receiver4_irq),       // receiver4.irq
		.sender_irq    (nios2_gen2_0_irq_irq)            //    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                         // reset_in0.reset
		.reset_in1      (nios2_gen2_0_debug_reset_request_reset), // reset_in1.reset
		.clk            (clk_clk),                                //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),         // reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req),     //          .reset_req
		.reset_req_in0  (1'b0),                                   // (terminated)
		.reset_req_in1  (1'b0),                                   // (terminated)
		.reset_in2      (1'b0),                                   // (terminated)
		.reset_req_in2  (1'b0),                                   // (terminated)
		.reset_in3      (1'b0),                                   // (terminated)
		.reset_req_in3  (1'b0),                                   // (terminated)
		.reset_in4      (1'b0),                                   // (terminated)
		.reset_req_in4  (1'b0),                                   // (terminated)
		.reset_in5      (1'b0),                                   // (terminated)
		.reset_req_in5  (1'b0),                                   // (terminated)
		.reset_in6      (1'b0),                                   // (terminated)
		.reset_req_in6  (1'b0),                                   // (terminated)
		.reset_in7      (1'b0),                                   // (terminated)
		.reset_req_in7  (1'b0),                                   // (terminated)
		.reset_in8      (1'b0),                                   // (terminated)
		.reset_req_in8  (1'b0),                                   // (terminated)
		.reset_in9      (1'b0),                                   // (terminated)
		.reset_req_in9  (1'b0),                                   // (terminated)
		.reset_in10     (1'b0),                                   // (terminated)
		.reset_req_in10 (1'b0),                                   // (terminated)
		.reset_in11     (1'b0),                                   // (terminated)
		.reset_req_in11 (1'b0),                                   // (terminated)
		.reset_in12     (1'b0),                                   // (terminated)
		.reset_req_in12 (1'b0),                                   // (terminated)
		.reset_in13     (1'b0),                                   // (terminated)
		.reset_req_in13 (1'b0),                                   // (terminated)
		.reset_in14     (1'b0),                                   // (terminated)
		.reset_req_in14 (1'b0),                                   // (terminated)
		.reset_in15     (1'b0),                                   // (terminated)
		.reset_req_in15 (1'b0)                                    // (terminated)
	);

endmodule
